1. Field of the Invention
The present invention relates to a gate-array large-scale integration (LSI) chip and more particularly to a gate-array LSI chip of a semiconductor integrated circuit in which input/output circuits can be formed within the internal area thereof so that the gate-array LSI chip can be cut into a plurality of chips each having any desired size and any desired number of gates.
2. Description of the Prior Art
Due to improvement in the integration degree of semiconductor integrated circuits, there has been a need to realize a gate-array LSI chip having any desired size and any desired number of gates.
Generally, in the internal area of a gate-array LSI chip, a number of gate-cell arrays extending in parallel and having wiring regions therebetween are provided for constructing desired circuits such as inverters, NAND gates, NOR gates, and so forth. On the periphery of the chip, protective input circuits, input/output buffers, and so forth are arranged for forming input/output pads and input/output circuits.
A conventional gate-array LSI chip does not have, in the internal area thereof, any region for forming an input/output pad or an input/output circuit. Therefore, it is not possible to cut the chip into a plurality of chips. Accordingly, chips obtained from one bulk pattern are all of the same size and have the same number of gates. When the required number of gates on one chip for forming a desired circuit is smaller than the actual number of gates on the same chip, some of the gates on the chip are not used. These unused gates are wasted and make the chip size unnecessarily large.